With shrinking dimensions of semiconductor devices such as power semiconductor switching devices, comparatively thin semiconductor wafers have to be handled in a process environment. With decreasing thickness of the semiconductor wafers trench structures including oxide layers and extending from the front side into the semiconductor wafer as well as thick metal layers on the wafer surface bend and warp the wafer to a significant degree. Wafer warping and wafer bowing increase process complexity, e.g., for a wafer dicing process that obtains separated semiconductor dies from a semiconductor wafer. During fabrication, auxiliary carriers and/or stress relaxing features at the front side may reduce wafer warpage and wafer bowing.
It is desirable to provide economic methods for manufacturing semiconductor devices that reduce wafer bowing and/or that simplify wafer dicing.